Author: animajoe0917

On August 4, 2026, two events occurred in the storage industry.

In the morning, SK Hynix and SanDisk released the first standard specification for **High Bandwidth Flash (HBF)** at FMS 2026—a brand new storage tier situated between HBM and SSD.

In the afternoon, TrendForce revealed: NVIDIA is evaluating a reduction in the HBM configuration of Rubin Ultra, changing from the originally planned 12hi HBM4E to a parallel evaluation of HBM4E 8hi, HBM4 12hi, and HBM4 8hi.

On the same day, Micron rose by +3.68%, SK Hynix by +3%, and SanDisk by +4.42%.

Two events, one direction: the supply bottleneck of HBM is being addressed, and new alternatives are being formally proposed. However, this is not a story of "the storage bull market is coming"; it is a story about the value distribution of storage being rewritten.

The key to this rewriting is not the advancement of NAND processes or breakthroughs in packaging technology—but rather interconnectivity.

In conclusion

Interconnectivity (optical + electrical + packaging) is becoming the primary bottleneck of AI infrastructure, with HBM following closely. DDR, HBF, CXL, and NAND each hold a position, but with decreasing priority. This is not a zero-sum alternative, but rather a migration of the bottleneck's geographic location—and the resulting re-evaluation of the entire storage system's value.

1. Core Proposition: The Bottleneck is Moving

In March 2026 GTC, NVIDIA launched the Vera Rubin platform. Two numbers define the new paradigm:

• NVLink 6 single GPU bidirectional bandwidth of 3.6 TB/s, which is double that of Blackwell

• NVL72 total interconnect bandwidth of 260 TB/s, fully connecting 72 Rubin GPUs + 36 Vera CPUs

But what's more interesting is not how much bandwidth has increased, but rather who has increased faster.

In the Blackwell era, single-card HBM3E bandwidth (8 TB/s) far exceeded NVLink 5 (1.8 TB/s), with the bottleneck in inter-chip communication. By the time of Vera Rubin, HBM4 bandwidth doubled to about 1.2 TB/s per card, but NVLink 6 more than doubled. More crucially— the cluster scale expanded from the thousand-card level to the hundred-thousand-card level, with the growth rate of inter-chip communication far surpassing that of single-card memory bandwidth.

From "can one card be fed" to "can a hundred thousand cards communicate well"—this is structural migration.

Evidence Level: ★★★★★ (GTC 2026 official data)

2. Seven Points on the Same Logical Chain

Connecting the key events from March to August 2026—

2026.3 GTC: NVLink 6 = 3.6 TB/s, 260 TB/s total rack bandwidth

2026.7 NVIDIA Spectrum-X CPO shipped → CPO mass production two years ahead of schedule

2026.7 New Fiber Optics H1 +78-103%, 1.6T acceleration Q3-Q4

2026.7 Intel EMIB-T released, MediaTek confirms dual routes (EMIB-T + CoWoS)

2026.8 TSMC reversely referred to EMIB, partnering with Jingshuo to develop EMIB-like packaging

2026.8 HBF standard released, UCIe directly connecting CPU/GPU, Google enters the fray

2026.8 NVIDIA evaluates reduction of HBM configuration

Each of these individually is newsworthy. Put together, they present seven facets of the same process:

• Interconnect bandwidth is accelerating (NVLink 6 → CPO shipments → 1.6T ramp-up)

• Packaging is breaking monopolies (EMIB-T challenging CoWoS, TSMC is also developing EMIB-like technology)

• HBM is being actively downgraded (the buyers with the most financial resources are cutting back)

• A new storage tier is emerging through interconnect buses (HBF + UCIe)

The name of the process is: the bottleneck is migrating from within computing units to the interconnect layer. Interconnect is not just about the wiring between GPUs in a data center—interconnect is becoming the hand that reorganizes the entire computing + storage pyramid.

3. Five-Layer Pyramid: Layer-by-Layer Analysis

Layer 1: Optical-Electrical Interconnect — Current Core Bottleneck ⭐⭐⭐⭐⭐

Why it matters now: The physical limits of copper interconnect have been pushed to extremes within the NVL72 rack; the next generation NVL144/NVL288 must incorporate light into the rack. The growth rate of interconnect bandwidth continues to outpace that of memory bandwidth—not about "solving the bottleneck," but about ongoing expansion on the highway.

Interconnect is the only track fulfilling all three conditions:

• Fastest growth (1.6T ramp-up + silicon photonics growth + CPO from 0 to 1)

• Most solid structure (the physical shift from copper to optics is one-way)

• Greatest selection space (optical modules, optical engines, silicon photonics, DSPs, switching chips, lasers—deep enough supply chain)

Risks: Valuation (Zhongji Xuchuang PE 81x TT P/E), physical limitations of silicon photonics, and CapEx growth inflection points.

Evidence Level: ★★★★★

Layer 2: Advanced Packaging — The Physical Foundation of Interconnect ⭐⭐⭐⭐☆

Why it matters now: The ultimate constraint on interconnect bandwidth lies not in cables or fibers, but in the physical wiring between chips. When the supply ceiling of packaging opens up directly determines the implementation speed of CPO + Chiplet mixed packaging.

TSMC CoWoS capacity is extremely tight. On July 30, The Information reported that TSMC is collaborating with Jingshuo Technology to develop a "EMIB-like" packaging solution—because the CoWoS silicon interposer solution is too costly and has insufficient capacity in large-scale Chiplet scenarios. TSMC's reverse reference to Intel's EMIB technology route already shows that the bottleneck of CoWoS has become so severe that alternative paths must be sought.

Intel EMIB-T is assaulting the castle. At the IEEE ECTC 2026, Intel showcased EMIB-T—introducing TSVs to achieve vertical power distribution in the silicon bridge. According to supply chain information, EMIB-T costs 50% less than CoWoS, yields 98%, and will be in mass production by 2027. MediaTek confirmed in its Q2 financial report that its AI ASIC project simultaneously uses both EMIB-T and CoWoS. More crucially—Intel 18A has secured AMD, NVIDIA, Marvell, Microsoft, Micron, and OpenAI as clients, with a yield of 85%.

Investment Implications: Packaging has transformed from a single dominant source to dual suppliers → Packaging capacity no longer chokes interconnect → CPO + Chiplet mixed packaging lands more quickly → Second-order catalysis of interconnect demand. The packaging chain does not directly purchase interconnect targets, but it determines when the supply ceiling of interconnect will open.

Evidence Level: ★★★★☆

Layer 3: HBM — Priced Bottleneck, Basic but Relaxing ⭐⭐⭐⭐

Why it matters now: HBM remains the "close memory" for AI GPUs, physically closest with the highest bandwidth, but supply constraints have evolved from a short-term bottleneck to a structural constraint—the marginal costs of increasing HBM capacity have begun to exceed the marginal benefits.

The three oligarchs (Samsung holds about 39% market share, SK Hynix, Micron) have a clear roadmap: HBM3E → HBM4 → HBM4E. BofA predicts the market will grow from approximately $350B in 2026 to $2,460B by 2030 (about 7 times).

However, the TrendForce report dated August 4 revealed a key turning point:

NVIDIA will change the HBM configuration of Rubin Ultra from 12hi HBM4E to a parallel assessment of HBM4E 8hi, HBM4 12hi, and HBM4 8hi starting Q3 2026. It’s not just NVIDIA; several CSPs are also considering reducing the HBM capacity of their self-developed ASICs.

Reason: The persistence of DRAM shortages extending into 2027 brings uncertainty about the verification progress of HBM4E 12hi. What does it mean when even the buyers with the most financial resources are proactively downgrading?

The supply constraints of HBM have evolved from a short-term bottleneck to a structural constraint.

HBM is still irreplaceable (inference batch=1 is latency-sensitive, and HBM bandwidth remains the primary constraint), but from an investment perspective:

• Growth patterns are linear improvements (stacked layers, TSV density), not architecture-level restructuring

• The oligopoly of three has been fully priced in

• When NVIDIA is cutting configurations and HBF is releasing standards next door— the scarcity of HBM is being doubly pressured

→ It has configuration value, but lacks excess elasticity.

Evidence Level: ★★★★★

Layer 4: HBF — A Whole New Thing, 0→1 ⭐★★★☆

Why it matters now: It is not coming to replace HBM. It is here to fill a gap created by HBM's high prices + low capacity. The essence of the "memory wall" in the inference era is a capacity wall rather than a bandwidth wall.

The first standard for HBF released on August 4 needs to be carefully dissected.

The logic of HBF: using NAND stacking for high bandwidth, tightly coupled to CPU/GPU through UCIe interconnect bus. HBM single stack capacity is 24-36 GB, while HBF is 512GB—a whole order of magnitude. HBM bandwidth is 1.2-2 TB/s, while HBF Grade 3 reaches 3.0 TB/s—higher than HBM4.

It is not here to replace HBM. It is here to solve a gap created by HBM's high prices + low capacity.

The essence of the "memory wall" in the inference era is a capacity wall rather than a bandwidth wall—KV Cache commonly runs into dozens to hundreds of GB, requiring large near-computation storage pools, not HBM's 8 TB/s limit bandwidth. HBF achieves high bandwidth with NAND at a cost of only a fraction of HBM, read-heavy and write-light, allowing for prefetching. Google DeepMind's entry is not just jumping on the bandwagon—they are the first to hit this wall with their own inference infrastructure.

The core significance for frameworks: The existence of HBF is not based on breakthroughs in NAND technology, but on breakthroughs in interconnect bus bandwidth. UCIe marks the penetration of interconnect architecture from rack-level to chip-level. Without UCIe, there is no HBF—it validates the ability of interconnect to redefine storage value.

Evidence Level: ★★★☆ (OCP official standard + alliance implementation, but at least 2 years away from mass production)

Beneficiaries of HBF:

• SanDisk ($SNDK): One of the dual protagonists in the HBF alliance, share price increased by 4600% after split, gross margin 78.4%—the market is not pricing NAND, but pricing "NAND redefined as an AI platform component."

• SK Hynix: Dual lines of NAND + HBM

• Micron ($MU): Benefit across all storage lines

• Domestic mapping: Yangtze Memory (NAND), Chipone/Annapurna (UCIe/Chiplet), but HBF packaging stacking requires extremely high standards, making it hard for short-term core chain entry.

Layer 5: CXL Memory Pools — Long-term Options for Interconnect Logic ⭐⭐⭐

Why it is suitable for tracking only now: CXL is not essentially about "more memory," but about pooling memory by decoupling it from servers through the interconnect bus—a natural extension of interconnect logic.

Latest Developments:

• Changxin Technology is the world's first to trial CXL 3.2 MXC chips (64GT/s), entering the Samsung/SK Hynix supply chain—Chinese controller chips first entering Korean manufacturers.

• Meta uses CXL to recycle old DDR4, reducing server footprint by 25%

• Marvell launches Tanzanite integrated end-to-end CXL platform

The logic is correct, but the ecological maturity is insufficient. CXL-aware OS/memory orchestration/application adaptation is still in early stages; true large-scale deployment is expected by 2027-2028. Suitable for tracking pools, but not for immediate orders at this price.

Evidence Level: ★★★ (Sufficient industry data, lacking observable revenue inflection points)

Below: DDR5 ⭐⭐⭐ / NAND ⭐⭐☆

DDR5 naturally increases with the number of host CPU cores in AI servers, showing no independent excess catalysis. NAND has independent cycle logic, training does not rely on storage bandwidth, and inference has incrementally increased demand for capacity rather than performance bottlenecks.

There is configuration value, but it is not on the priority line of the "bottleneck migration" framework.

4. Investment Mapping

Marvell ($MRVL) deserves a special mention. It spans DSP + Teralynx switching chips + custom ASICs + CXL, serving as a full-stack provider of interconnect infrastructure. Teralynx 10 (3nm, 100.4 Tb/s) and custom ASICs have not been adequately priced by the market yet—if interconnect is the main line, Marvell's configuration value is comparable to optical modules themselves.

5. Risk Warning

• HBF is a specification, not a product: It may take until 2028 for large-scale shipments, with 2026-2027 primarily driven by narrative rather than performance validation. The valuation of SanDisk's 4600% increase + 78.4% gross margin needs to be continuously verified.

• AI CapEx cycle inflection point: If CapEx growth drops below $700B+ in 2027, both interconnect and HBM growth rates will be impacted.

• Technical route risks: Silicon photonic modulators are nearing physical limits, and the next generation optical modulation technology (thin film lithium niobate/polymer) is not yet mature.

• Valuation risks: Zhongji Xuchuang PE 81x, New Fiber Optics PE 65x; current valuation implies continuous unexpected ramp-up. If the 1.6T ramp or silicon photonic progress falls short of expectations, elasticity will quickly converge.

• Geopolitical issues: If export controls on optical modules/optical engines escalate, A-share targets (Zhongji Xuchuang, New Fiber Optics, Tianfu) will be the first affected; U.S. stock targets ( $COHR, $LITE, $AAOI, $MRVL, $AVGO) are relatively more diversified.

免责声明：本文章仅代表作者个人观点，不代表本平台的立场和观点。本文章仅供信息分享，不构成对任何人的任何投资建议。用户与作者之间的任何争议，与本平台无关。如网页中刊载的文章或图片涉及侵权，请提供相关的权利证明和身份证明发送邮件到support@aicoin.com，本平台相关工作人员将会进行核查。